1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a transistor and a method for fabricating the same, capable of increasing a driving current while raising a threshold voltage.
2. Description of the Prior Art
Recently, as semiconductor devices have been highly integrated, channel lengths of transistors are significantly shortened. Such a phenomenon may occur in a DRAM cell, so that a short channel effect causing a threshold voltage to be significantly lowered is seriously represented in a planar transistor structure.
If the threshold voltage of a transistor becomes lowered, a relatively great amount of current is leaked through channels of the transistor even if the transistor is not turned on, so electric charges stored in a DRAM capacitor are gradually discharged, thereby causing data loss.
In order to solve the above problem, Vt implantation (threshold voltage ion implantation) is carried out to implant B or BF2 into a silicon substrate. In general, the Vt implantation must be performed while increasing the density of B or BF2 as a width of a semiconductor device becomes narrowed.
However, if the Vt implantation is carried out while increasing the density of B or BF2, a width of a depletion region connected to a junction region becomes reduced, so that an electric field applied to the depletion region is increased, thereby increasing the junction leakage current.
Thus, it is necessary for a DRAM device to develop a technique capable of stably storing electric charges in a capacitor even if the channel width of the transistor becomes reduced. To this end, there has been suggested a technique for enlarging a channel length, in which a predetermined portion of a silicon substrate corresponding to a channel area of a transistor is etched by a predetermined depth in order to enlarge the channel length.
FIG. 1 is a plan view illustrating a transistor having a recess gate structure, in which a silicon substrate is etched so as to enlarge a channel length, and FIGS. 2 and 3 are sectional views taken along lines II-II and III-III shown in FIG. 1, respectively. Reference numerals 1 to 4 represent a silicon substrate, an isolation layer, a recess gate and a junction area, respectively.
However, the transistor having the recess gate causes higher back bias dependency of a threshold voltage so that the threshold voltage may easily vary even if the back bias shows little variation. For this reason, the transistor having the recess gate may not ensure operational reliability thereof.
Another problem may occur with the increase of the integration degree of the semiconductor device. That is, the driving current of the transistor may be reduced as the width of the transistor becomes narrowed. In order to improve the driving current of a two-dimensional transistor, a fin FET (field effect transistor) structure, in which a predetermined portion of a silicon substrate is protruded as shown in FIG. 4, has been developed.
According to the fin FET structure, three surfaces of the protruded silicon substrate are used as channels for the transistor, so that the driving current of the transistor can be increased while lowering the back bias dependency of the threshold voltage. In FIG. 4, reference numerals 41, 43 and 44 represent a silicon substrate, a gate and a junction area, respectively.
However, if the fin FET structure is applied to the DRAM device, data retention time may be shortened.
In short, the conventional recess gate structure and fin FET structure may present limitations to increase the driving current while raising the threshold voltage.